Measurement circuit and electronic device

ABSTRACT

Provided is a measurement circuit that is provided in the same electronic device as a circuit under measurement, comprises a difference generating section and an integrating section, and performs a sigma-delta AD conversion on a signal under measurement output by the circuit under measurement, the measurement circuit further comprising a sampling section that is provided between an output end of the difference generating section and an input end of the integrating section, detects a level of a signal input thereto at predetermined sampling intervals, and outputs a sampled signal corresponding to the detected signal level. This measurement circuit is used to easily perform a sigma-delta AD conversion on a high-frequency signal under measurement.

BACKGROUND

1. Technical Field

The present invention relates to a measurement circuit and an electronicdevice.

2. Related Art

An effective technique for checking the operation of a circuit inside anelectronic device, such as an LSI, is to measure a signal output by thecircuit. If the signal has a high frequency, however, the signalwaveform is distorted when the signal is drawn outside the electronicdevice. Therefore, it is difficult to directly measure the change timingor the like of the signal itself. Furthermore, an EB (Electronic Beam)tester is known as a means for measuring operations, such as changetiming, of a signal in a circuit in an electronic device.

The Non-Patent Document shown below is provided as related art.Non-Patent Document 1: Makoto Nagata, “On-Chip MeasurementsComplementary to Design Flow for Integrity on SoCs,” Proc. DesignAutomation Conference 2007, pp. 400-403, 2007.06.

When using an external device, such as an EB tester, to measure aninternal signal of a circuit under test, it is necessary to purchase theexternal device equipment, and the measurement takes a long time.Another measurement method involves providing an additional circuit thatconverts the internal signal within the electronic device into alow-frequency signal, and then measuring the low-frequency signal on theoutside. The frequency of the signal can be converted by a mixer or thelike. However, since the additional circuit increases the overallcircuit size, the cost of the electronic device also increases.

SUMMARY

Therefore, it is an object of an aspect of the innovations herein toprovide a measurement circuit and an electronic device, which arecapable of overcoming the above drawbacks accompanying the related art.The above and other objects can be achieved by combinations described inthe independent claims. According to a first aspect related to theinnovations herein, provided is a measurement circuit that is providedin the same electronic device as a circuit under measurement, comprisesa difference generating section and an integrating section, and performsa sigma-delta AD conversion on a signal under measurement output by thecircuit under measurement, the measurement circuit further comprising asampling section that is provided between an output end of thedifference generating section and an input end of the integratingsection, detects a level of a signal input thereto at predeterminedsampling intervals, and outputs a sampled signal corresponding to thedetected signal level. Also provided is an electronic device includingthe measurement circuit.

The summary clause does not necessarily describe all necessary featuresof the embodiments of the present invention. The present invention mayalso be a sub-combination of the features described above.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an exemplary configuration of an electronic device 200.

FIG. 2 shows exemplary waveforms of each signal in the sampling section20.

FIG. 3 shows another exemplary configuration of the measurement circuit100.

FIG. 4 shows exemplary waveforms of each signal in the measurementcircuit 100 described in relation to FIG. 3.

FIG. 5 shows another exemplary configuration of the measurement circuit100.

FIG. 6 shows another exemplary configuration of the measurement circuit100.

FIG. 7 shows another exemplary configuration of the measurement circuit100.

FIG. 8 shows another exemplary configuration of the measurement circuit100.

FIG. 9 shows exemplary frequency characteristics of the sampling section20.

FIG. 10 shows frequency characteristics of the output from a final-stagesampling section 20-n with respect to the input to a first-stagesampling section 20-1.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

Hereinafter, some embodiments of the present invention will bedescribed. The embodiments do not limit the invention according to theclaims, and all the combinations of the features described in theembodiments are not necessarily essential to means provided by aspectsof the invention.

FIG. 1 shows an exemplary configuration of an electronic device 200. Theelectronic device 200 may be a semiconductor chip or the like. Theelectronic device 200 includes a circuit under measurement 108, ameasurement circuit 100, an input terminal 102, an output terminal 104,and a measuring terminal 106.

The circuit under measurement 108 refers to an actual operation circuitthat, when the electronic device 200 is implemented in an electricdevice or the like, performs at least a portion of the functions of theelectric device. The circuit under measurement 108 operates according toan input signal to output a signal corresponding to the operationresult.

The circuit under measurement 108 may receive a pattern from outside theelectronic device 200, via the input terminal 102. The output terminal104 outputs, to the outside of the electronic device 200, the signaloutput by the circuit under measurement 108. The circuit undermeasurement 108 receives an operational clock Tsck with a period ofTsck. The operational clock Tsck may be input from outside theelectronic device 200, or may be generated within the electronic device200. The circuit under measurement 108 outputs a signal insynchronization with the operational clock Tsck.

The measurement circuit 100 is provided within the same electronicdevice 200 as the circuit under measurement 108. The measurement circuit100 measures a signal under measurement output by the circuit undermeasurement 108, and outputs the measurement results to the outside ofthe electronic device 200. When measuring the signal under measurementoutput by the circuit under measurement 108, the circuit undermeasurement 108 outputs the signal under measurement with a repeatingprescribed signal pattern and a period Fout that is an integer multipleof the operational clock Tsck. The circuit under measurement 108 mayreceive, from an external device, an input pattern for outputting thesignal under measurement.

The measurement circuit 100 outputs the measurement result as a signalwhose frequency is lower than the Nyquist frequency of the signal undermeasurement. The Nyquist frequency of the signal under measurement isexpressed as 1/(2×Fout). More specifically, the measurement circuit 100measures the signal under measurement by performing a sigma-delta ADconversion, with a frequency lower than the Nyquist frequency of thesignal under measurement, on the signal under measurement output fromthe circuit under measurement 108.

The sigma-delta AD conversion can aggregate, in a high frequency region,the noise components caused by the quantization error of the ADconversion. With a normal sigma-delta AD conversion, however, the ADconversion is performed by integrating the signal level of the signalunder measurement and comparing the integrated value to a referencelevel at each pulse timing of a measurement clock. Therefore, in thesigma-delta AD conversion, the signal level of the signal undermeasurement must not change significantly between pulses of themeasurement clock. In other words, with the sigma-delta AD conversion,the frequency of the measurement clock must be sufficiently higher thanthe frequency of the signal under measurement.

The measurement circuit 100 measures the signal under measurement byperforming the sigma-delta AD conversion with a frequency lower than theNyquist frequency of the signal under measurement. As a result, ahigh-frequency signal under measurement can be easily subjected to thesigma-delta AD conversion without generating a high-frequencymeasurement clock.

The measurement circuit 100 of the present embodiment includes adifference generating section 10, a sampling section 20, an integratingsection 30, a quantizing section 40, and a feedback section 50. Thedifference generating section 10, the integrating section 30, thequantizing section 40, and the feedback section 50 form the so-calledsigma-delta AD converter. The difference generating section 10 decreasesthe signal level of the signal under measurement from the circuit undermeasurement 108, according to a feedback signal FB received from thefeedback section 50, and inputs the resulting signal to the samplingsection 20.

The sampling section 20 is provided between the output end of thedifference generating section 10 and the input end of the integratingsection 30. The sampling section 20 detects, at predetermined samplingintervals, the level of the signal received from the differencegenerating section 10. The sampling section 20 outputs a sampled signalcorresponding to the signal level detected in each sampling interval. Inthe present embodiment, the sampling section 20 includes a sample/holdcircuit. The sampling section 20 of the present embodiment outputs, asthe sampled signal, a hold signal HS that is obtained by holding thesignal level detected in each sampling interval for a prescribedduration corresponding to the sampling interval. The sampling section 20detects the signal level output by the difference generating section 10,with an operational period greater than the repeating period Fout of thesignal under measurement.

For example, the sampling section 20 may detect the level of thereceived signal at a timing corresponding to each pulse of themeasurement clock Tcck. The measurement clock Tcck may be received fromoutside the electronic device 200, or may be generated within theelectronic device 200. The measurement clock Tcck has a frequency thatis lower than the Nyquist frequency of the signal under measurement. Thesampling section 20 outputs a hold signal HS obtained by holding thesignal level detected according to each pulse of the measurement clockTcck until the next pulse timing of the measurement clock Tcck.

The measurement clock Tcck and the repeating frequency Fout of thesignal under measurement have the relationship shown below.

Tcck×m=Fout×n+Trck

Here, m and n are natural numbers. As a result, for every m cycles ofthe measurement clock Tcck, the relative phase between the measurementclock and the signal under measurement changes by Trck. In other words,the sampling section 20 can detect the signal level of the signal undermeasurement at a timing shifted by Trck for every m cycles of themeasurement clock Tcck. Therefore, the signal under measurement can beequivalently sampled with the time resolution Trck, by arranging thesampled data of the signal under measurement for every m cycles of themeasurement clock Tcck.

The integrating section 30 integrates, on the time axis, the signallevel of the hold signal HS output from the sampling section 20. Theintegrating section 30 is a circuit that integrates the signal level ofa received analog signal on the time axis.

The quantizing section 40 outputs a digital signal corresponding to theintegrated value from the integrating section 30. The quantizing section40 may detect the value of the integration result from the integratingsection 30 with the same period as the operational period of thesampling section 20, and output a digital signal corresponding to thedetected value. The quantizing section 40 performs quantization by ADconverting the integrated value at a timing of each pulse of themeasurement clock Tcck.

When the quantizing section 40 outputs the digital signal, the feedbacksection 50 inputs to the difference generating section 10 the feedbacksignal FB with a signal level corresponding to the digital signal. As aresult, the noise caused by the quantization error of the quantizingsection 40 is decreased. The feedback section 50 of the presentembodiment includes a delaying section 52 and a DA converter 54.

The delaying section 52 is provided in parallel with the measuringterminal 106 and delays the digital signal output by the quantizingsection 40. The delaying section 52 may delay the digital signal by oneperiod of the measurement clock Tcck. The delaying section 52 mayinclude a flip-flop that is supplied with the measurement clock Tcck asthe operational clock. The DA converter 54 outputs the feedback signalFB obtained by DA converting the digital signal delayed by the delayingsection 52.

The measurement circuit 100 may output the measurement result via themeasuring terminal 106, or may output the measurement result via theoutput terminal 104. The measurement circuit 100 may output, as themeasurement result, a digital signal obtained by performing thesigma-delta AD conversion on the signal under measurement, or an analogsignal generated from this digital signal. The measurement circuit 100may extract a component of this digital signal that is less than orequal to a predetermined frequency, and output this component. In thiscase, the measurement circuit 100 may include a low-pass filter forpassing the digital signal.

FIG. 2 shows exemplary waveforms of each signal in the sampling section20. In the present embodiment, the period of the measurement clock Tcckis greater than the repeating period Fout of the signal undermeasurement by Trck. In the example of FIG. 2, Tcck=Fout+(Fout/8).

As described above, the sampling section 20 outputs the hold signal HSobtained by holding the signal level of the signal under measurementaccording to the pulses of the measurement clock Tcck. As a result, thesampling section 20 outputs a digital waveform with a period obtained asthe product of (i) the period of the signal under measurement and (ii)the ratio between Trck and Fout. In the example of FIG. 2, the samplingsection 20 outputs a digital waveform with a period that is eight timesthe period of the signal under measurement.

Since the integrating section 30 integrates the hold signal HS, which isobtained by holding the signal level of the signal under measurement atthe timing of the measurement clock, the integrated value correspondingto the signal level of the signal under measurement at the timing of themeasurement clock can be output, even if the signal level of the signalunder measurement changes. The quantizing section 40 quantizes thisintegrated value, and therefore the digital signal corresponding to thesignal level of the signal under measurement at the timing of themeasurement clock can be output.

Even if the sampling section 20 is provided between the circuit undermeasurement 108 and the difference generating section 10, thesigma-delta AD conversion can be performed on the signal undermeasurement with the low-frequency measurement clock Tcck. It should benoted that, in this case, the sampling section 20 directly receives thesignal under measurement output by the circuit under measurement 108,and therefore it is preferable that the sampling section 20 be capableof operating across the entire voltage range of the signal undermeasurement.

On the other hand, when the sampling section 20 is provided between thedifference generating section 10 and the integrating section 30 as shownin FIG. 1, the sampling section 20 is provided with a signal obtained bydividing the signal under measurement by the feedback signal FB, andtherefore the necessary operational voltage range is decreased. As aresult, the sampling section 20 is preferably provided between thedifference generating section 10 and the integrating section 30.

FIG. 3 shows another exemplary configuration of the measurement circuit100. Components in FIG. 3 having the same reference numerals ascomponents in FIG. 1 may have the same function and configuration asthese components. The measurement circuit 100 includes a resistor 12, aresistor 14, a difference generating section 10, a sampling section 20,an integrating section 30, a quantizing section 40, and a delayingsection 52.

The difference generating section 10 receives the signal undermeasurement via the resistor 12 and receives the feedback signal FB viathe resistor 14. The difference generating section 10 may be aconnection line electrically connected to the resistor 12 and theresistor 14. In this case, the feedback signal FB has a negative signand the difference generating section 10 adds the negative feedbacksignal FB to the signal under measurement.

The sampling section 20 includes a first transistor 22 and a secondtransistor 24, whose sources are connected in parallel relative to thedifference generating section 10, and a pulse generating section 26. Thefirst transistor 22 and the second transistor 24 have the samecharacteristics.

The pulse generating section 26 receives the measurement clock Tcck andadjusts the pulse width of each pulse of the measurement clock Tcck tobe a predetermined pulse width. For example, the pulse generatingsection 26 may output an exclusive OR of the measurement clock and adelayed clock, which is obtained by delaying the measurement clock Tcckaccording to the pulse width to be generated. The pulse generatingsection 26 supplies the generated pulse to the gate of the secondtransistor 24 and supplies an inverse pulse, obtained by inverting thegenerated pulse, to the gate of the first transistor 22. In other words,the first transistor 22 and the second transistor 24 operatedifferentially.

Generally, a capacitor for holding an output voltage is provided in thesample/hold circuit, but in the measurement circuit 100 of the presentembodiment, a capacitor 32 functioning as the integrating section 30 isprovided downstream from the sampling section 20. The capacitor 32 has afunction to hold the output of the sampling section 20, and thereforethe sampling section 20 need not include a capacitor.

The integrating section 30 includes a capacitor 32 between the firsttransistor 22 and the second transistor 24. As a result, the integratingsection 30 integrates the voltage output by the sampling circuit 20.

The quantizing section 40 outputs a digital signal corresponding to thevoltage across the capacitor 32. The quantizing section 40 of thepresent embodiment compares the voltage across the capacitor 32 to apredetermined reference level, at the pulse timing of the measurementclock Tcck. The quantizing section 40 may be a 1-bit AD converter thatoutputs a pulse when the voltage across the capacitor 32 is greater thanor equal to the reference level.

The delaying section 52 includes a flip-flop that receives the pulseoutput by the quantizing section 40 at a data input terminal D andreceives the measurement clock Tcck at a clock input terminal. Thedelaying section 52 delays the pulse received from the quantizingsection 40 according to the measurement clock Tcck, and outputs thedelayed pulse from an output terminal Q. The delaying section 52 delaysthe pulse received from the quantizing section 40 according to themeasurement clock Tcck, inverts the pulse, and outputs the resultingpulse from the inverted output terminal /Q.

The amplitude level of the pulse output from the inverted outputterminal /Q may be the same as the reference level in the quantizingsection 40. The inverted output terminal /Q inputs this inverted pulseto the difference generating section 10 as the feedback signal FB.

FIG. 4 shows exemplary waveforms of each signal in the measurementcircuit 100 described in relation to FIG. 3. In FIG. 4, the signal undermeasurement is represented by the dashed-line triangular wave and theoutput of the integrating section 30 is represented by the solidstraight line. The pulse generating section 26 outputs a signal with apredetermined pulse width having the same period as the measurementclock Tcck.

While the pulse received from the pulse generating section 26 is logicH, the second transistor 24 charges and discharges the capacitor 32according to the signal under measurement. The integrating section 30outputs the voltage across the capacitor 32.

The quantizing section 40 compares the voltage output by the integratingsection 30 to a reference level. The quantizing section 40 may performthis comparison while the signal input to the gate of the secondtransistor 24 is logic L. With this operation, the pulses can be outputaccording to the signal level of the signal under measurement at thetiming of the measurement clock.

It should be noted that Trck, e.g. the difference between the repeatingperiod Fout of the signal under measurement and the period of themeasurement clock Tcck, is preferably sufficiently smaller than therepeating period Fout of the signal under measurement. For example, Trckmay be 1/1000 or less of the repeating period Fout. The ratio betweenTrck and the repeating frequency Fout of the signal under measurementmay be approximately equal to the ratio between the sampling period inthe sigma-delta AD conversion and the repeating period Fout of thesignal under measurement. The width of the pulses output by the pulsegenerating section 26 may be greater than or less than Trck.

FIG. 5 shows another exemplary configuration of the measurement circuit100. The measurement circuit 100 of the present embodiment includes adifference generating section 10, a sampling section 20, an integratingsection 30, a quantizing section 40, a feedback section 50, and an errorcalculating section 60. Components in FIG. 5 having the same referencenumerals as components in FIG. 1 or FIG. 3 may have the same functionand configuration as these components.

The difference generating section 10 is the same as the differencegenerating section 10 described in FIGS. 1 to 4. The quantizing section40 outputs a pulse when the signal level of the signal output by thedifference generating section 10 is greater than or equal to apredetermined reference level. In the same manner as the quantizingsection 40 described in FIG. 1, the quantizing section 40 may output amulti-bit digital signal. In this case, the feedback section 50 mayinclude a DA converter 54.

The sampling section 20 is provided in parallel with the quantizingsection 40, and outputs a hold signal HS corresponding to the signaloutput by the difference generating section 10. The differencegenerating section 10 is electrically connected to the quantizingsection 40 and the sampling section 20 via a branching path 70. Thebranching path 70 branches the signal output from the differencegenerating section 10 and inputs the resulting signals to the quantizingsection 40 and the sampling section 20. The signal input to the samplingsection 20 is then input to the error calculating section 60 throughprocessing of the sampling section 20.

The operation of the sampling section 20 may be the same as that of thesampling section 20 described in relation to FIG. 2. The samplingsection 20 and the quantizing section 40 receive the measurement clockTcck with the same period.

The error calculating section 60 calculates a difference between adigital value corresponding to the pulse output by the quantizingsection 40 and the signal level output by the difference generatingsection 10. The error calculating section 60 may calculate the voltagecorresponding to the difference between the level of the signal outputby the difference generating section 10 and a reference level of thequantizing section 40, according to the pulse output by the quantizingsection 40.

The integrating section 30 integrates the error calculated by the errorcalculating section 60. The integrating section 30 integrates thevoltage output by the error calculating section 60 on the time axis. Thefeedback section 50 inputs to the difference generating section 10 thefeedback signal FB having a signal level corresponding to the integratedvalue from the integrating section 30.

The measurement circuit 100 of the present embodiment, which performs asigma-delta AD conversion that involves the integrating section 30integrating the quantization error, can easily perform the sigma-deltaAD conversion on a high-frequency signal under measurement, in the samemanner as the measurement circuit 100 described in relation to FIGS. 1to 4, by including the sampling section 20 between the differencegenerating section 10 and the integrating section 30.

FIG. 6 shows another exemplary configuration of the measurement circuit100. The measurement circuit 100 of the present embodiment differs fromthe measurement circuit 100 shown in FIG. 5 in that the location of thesampling section 20 is different. The remaining configuration may be thesame as that of the measurement circuit 100 shown in FIG. 5.

The measurement circuit 100 of the present embodiment includes thesampling section 20 between the output end of the difference generatingsection 10 and the branching path 70. The sampling section 20 inputs thehold signal, corresponding to the signal output by the differencegenerating section 10, to both the quantizing section 40 and the errorcalculating section 60.

With this configuration as well, the sigma-delta AD conversion can beeasily performed on a high-frequency signal under measurement. It shouldbe noted that providing the sampling section 20 at the position shown inFIG. 6 causes the hold signal HS to be input to the quantizing section40, and so the loop band in the sigma-delta AD conversion is determinedby the frequency characteristics of the sampling section 20. Therefore,in the example of FIG. 6, the sampling section 20 preferably hasfrequency characteristics including a wider frequency band.

As shown in FIG. 5, when the sampling section 20 is provided in parallelwith the quantizing section 40 between the output end of the differencegenerating section 10 and the input end of the error calculating section60, the frequency characteristics of the sampling section 20 do notaffect the loop band in the sigma-delta AD conversion. Therefore, whenthere is no limitation on the arrangement of the circuit elements, thesampling section 20 is preferably provided in parallel with thequantizing section 40 between the output end of the differencegenerating section 10 and the input end of the error calculating section60.

FIG. 7 shows an exemplary configuration of another measurement circuit100. The measurement circuit 100 of the present embodiment differs fromthe measurement circuit 100 shown in FIG. 5 in that the position of thesampling section 20 is different. The remaining configuration may be thesame as that of the measurement circuit 100 shown in FIG. 5.

The measurement circuit 100 of the present embodiment includes thesampling section 20 between the output end of the error calculatingsection 60 and the input end of the integrating section 30. The samplingsection 20 outputs a hold signal corresponding to the signal output bythe error calculating section 60. The integrating section 30 integratesthe hold signal output by the sampling section 20. With thisconfiguration as well, the sigma-delta AD conversion can be easilyperformed on a high-frequency signal under measurement.

FIG. 8 shows another exemplary configuration of the measurement circuit100. The measurement circuit 100 of the present embodiment differs fromthe measurement circuits 100 described in FIGS. 1 to 7 by including aplurality of sampling sections 20 connected in cascade instead of asingle sampling section 20. The remaining configuration may be the sameas that of any one of the measurement circuits 100 described in relationto FIGS. 1 to 7. FIG. 8 shows a measurement circuit 100 resulting fromthe inclusion of the plurality of sampling sections 20 connected incascade in the configuration shown in FIG. 5.

Each sampling section 20 has a different aperture time for acquiring thelevel of the received signal. Each sampling section 20 may average orintegrate the signal level of the signal under measurement over a timeperiod from when the pulse of the measurement clock Tcck is received towhen the aperture time has passed, and output the result. For example,in the example described in FIGS. 3 and 4, the aperture time correspondsto the width of the pulse output by the pulse generating section 26.

FIG. 9 shows exemplary frequency characteristics of the sampling section20. In FIG. 9, the horizontal axis represents frequency and the verticalaxis represents gain. When the sampling section 20 averages orintegrates the signal level of the signal under measurement within anaperture time, as described above, a signal whose signal period is equalto one divided by an integer multiple of the aperture time receives again of 0 from the sample/hold section 20.

In other words, for a signal whose signal period is equal to one dividedby an integer multiple of the aperture time, the sampling section 20does not change the output value no matter which timing is used for thesampling. Therefore, as shown in FIG. 9, the output gain of thesample/hold section 20 is 0 at a frequency that is an integer multipleof the frequency fa corresponding to the aperture time Ta, wherefa=1/Ta.

FIG. 10 shows frequency characteristics of the output from a final-stagesampling section 20-n with respect to the input to a first-stagesampling section 20-1. When a plurality of sampling sections 20 havingslightly different aperture times are connected in cascade, a notchedportion of the frequency characteristic is continuous, and therefore inthe overall frequency characteristic, the output gain becomessubstantially zero within a specific frequency range. The aperture timesof the sampling sections 20 may be set such that the notch frequenciesof the sampling sections 20 are uniformly distributed betweenpredetermined frequencies fal and fan. The aperture time of eachsampling section 20 may be changeable.

With this configuration, the sampling sections 20 can function as a bandpass filter. Therefore, the loop band or the like in the sigma-delta ADconversion can be controlled, for example.

In the examples of FIGS. 1 to 10, the measurement circuit 100 isprovided on the same electronic device 200 as the circuit undermeasurement 108, but as another example, the measurement circuit 100 maybe provided in a different device than the circuit under measurement108.

While the embodiments of the present invention have been described, thetechnical scope of the invention is not limited to the above describedembodiments. It is apparent to persons skilled in the art that variousalterations and improvements can be added to the above-describedembodiments. It is also apparent from the scope of the claims that theembodiments added with such alterations or improvements can be includedin the technical scope of the invention.

The operations, procedures, steps, and stages of each process performedby an apparatus, system, program, and method shown in the claims,embodiments, or diagrams can be performed in any order as long as theorder is not indicated by “prior to,” “before,” or the like and as longas the output from a previous process is not used in a later process.Even if the process flow is described using phrases such as “first” or“next” in the claims, embodiments, or diagrams, it does not necessarilymean that the process must be performed in this order.

1. A measurement circuit that is provided in the same electronic deviceas a circuit under measurement, comprises a difference generatingsection and an integrating section, and performs a sigma-delta ADconversion on a signal under measurement output by the circuit undermeasurement, the measurement circuit further comprising: a samplingsection that is provided between an output end of the differencegenerating section and an input end of the integrating section, detectsa level of a signal input thereto at predetermined sampling intervals,and outputs a sampled signal corresponding to the detected signal level.2. The measurement circuit according to claim 1, further comprising aquantizing section and a feedback section, wherein the differencegenerating section decreases a signal level of the signal undermeasurement according to a feedback signal input thereto, and inputs theresulting signal to the sampling section, the integrating sectionintegrates the signal level of the sampled signal output by the samplingsection, the quantizing section outputs a digital signal correspondingto the integrated value from the integrating section, and when thequantizing section outputs the digital signal, the feedback sectioninputs to the difference generating section the feedback signal with asignal level corresponding to a value of the digital signal.
 3. Themeasurement circuit according to claim 1, further comprising aquantizing section, a feedback section, and an error calculatingsection, wherein the difference generating section decreases a signallevel of the signal under measurement according to a feedback signalinput thereto, and outputs the resulting signal, the quantizing sectionoutputs a digital signal corresponding to a signal level of a signaloutput by the difference generating section, the error calculatingsection calculates an error between the level of the signal output bythe difference generating section and a value of the digital signal, theintegrating section integrates the error calculated by the errorcalculating section, and the feedback section inputs to the differencegenerating section the feedback signal with a signal level correspondingto the integrated value from the integrating section.
 4. The measurementcircuit according to claim 3, wherein the sampling section is providedbetween an output end of the difference generating section and an inputend of the error calculating section.
 5. The measurement circuitaccording to claim 3, further comprising a branching path that branchesthe signal output by the difference generating section and inputs theresulting signals to the quantizing section and the error calculatingsection, wherein the sampling section is provided between the branchingpath and an input end of the error calculating section.
 6. Themeasurement circuit according to claim 2, wherein the sampling sectiondetects the signal level output by the difference generating section,with an operational period that is greater than a period of the signalunder measurement.
 7. The measurement circuit according to claim 6,wherein the quantizing section detects a value of the integration resultfrom the integrating section, with a period equal to the operationalperiod of the sampling section, and outputs a digital signalcorresponding to the detected value.
 8. The measurement circuitaccording to claim 2, comprising a plurality of the sampling sectionsthat are connected in cascade and that each have a different aperturetiming for acquiring a level of a signal input thereto.
 9. Themeasurement circuit according to claim 1, wherein the sampling sectionoutputs a sampled signal obtained by holding the signal level detectedat each sampling interval for a time period corresponding to thesampling interval.
 10. An electronic device comprising: the measurementcircuit according to claim 1; and the circuit under measurement.
 11. Ameasurement circuit that comprises a difference generating section andan integrating section and that performs a sigma-delta AD conversion ona signal under measurement, the measurement circuit further comprising:a sampling section that is provided between an output end of thedifference generating section and an input end of the integratingsection, detects a level of a signal input thereto at predeterminedsampling intervals, and outputs a sampled signal obtained by holding thesignal level detected at each sampling interval for a time periodcorresponding to the sampling interval.